1. Field of the Invention
The present invention relates to a field-effect transistor, a semiconductor device including the field-effect transistor, and a method of producing a semiconductor device.
2. Description of the Related Art
Monolithic microwave integrated circuits (MMICs) composed of a compound semiconductor having a satisfactory high-frequency property are used for RF transmission/reception circuits for transmitting and receiving radio frequency (RF) signals in cell phones.
Among these MMICs, power amplifier modules for amplifying signals for transmission have extremely large electric power consumption. As a recent demand for reducing the electric power consumption in cell phones has increased, MMICs have also been desired to have lower electric power consumption. Accordingly, power amplifier modules having high gain, high power-added efficiency, and low electric power consumption have been desired.
In order to meet such a demand, a junction pseudomorphic high-electron-mobility transistor (JPHEMT), which is a known example of a transistor suitable for high gain and high power-added efficiency, is often used as a field-effect transistor for power amplifier modules.
More specifically, for example, the junction pseudomorphic high-electron-mobility transistor has the following structure. As shown in FIG. 23, a semiconductor layer is provided on a semi-insulating GaAs (gallium arsenide) substrate 110. The semiconductor layer is formed by forming a buffer layer 111 composed of an undoped GaAs film, a channel layer 112 composed of an undoped InGaAs (indium-gallium-arsenide) film, a spacer layer 113 composed of an undoped AlGaAs (aluminum-gallium-arsenide) film, a doping layer 114 composed of an n-type AlGaAs film, and a barrier layer 115 composed of an n-type AlGaAs film, in that order, by epitaxial growth. A buried gate region 116 is provided in the barrier layer 115 directly under a gate electrode-forming area by doping a p-type impurity such as zinc. An insulating film 117 composed of a silicon nitride film or the like is provided on the top surface of the barrier layer 115. An opening 118s for a source electrode, an opening 118d for a drain electrode, and an opening 118g for a gate electrode are provided on the insulating film 117. A source electrode 119s, a drain electrode 119d, and a gate electrode 119g are provided in the opening 118s for a source electrode, the opening 118d for a drain electrode, and the opening 118g for a gate electrode, respectively.
In this junction pseudomorphic high-electron-mobility transistor, in general, the gain characteristic can be improved by decreasing the source parasitic resistance Rs, decreasing the gate resistance Rg, increasing the mutual conductance gm, or decreasing the parasitic capacitance Cgd between the gate and the drain (hereinafter referred to as gate-drain parasitic capacitance Cgd). It is believed that a decrease in the gate-drain parasitic capacitance Cgd is particularly effective.
In order to decrease the gate-drain parasitic capacitance Cgd, the distance Lgd between the gate electrode and the drain electrode may be increased. However, an increase in the distance Lgd between the gate electrode and the drain electrode increases the size of the junction pseudomorphic high-electron-mobility transistor, resulting in an increase in the chip area. Since this is contrary to the demand for miniaturization, the increase in the distance Lgd is not a practical measure. Furthermore, when the distance Lgd between the gate electrode and the drain electrode is increased, the on-resistance of the junction pseudomorphic high-electron-mobility transistor is increased and thus the power-added efficiency may be decreased.
The gate-drain parasitic capacitance Cgd can also be decreased by decreasing a channel concentration, which is the concentration of an impurity doped in the doping layer 114. In this case, however, the source parasitic resistance Rs, which is the resistance between the source and the gate, is increased, and therefore the gain may be decreased. Furthermore, when the channel concentration is decreased, the on-resistance of the junction pseudomorphic high-electron-mobility transistor is increased. Accordingly, the power-added efficiency may be decreased.
Consequently, for example, according to a technique disclosed in Japanese Unexamined Patent Application Publication No. 2003-59947, a recessed part is provided on the top surface of a barrier layer at a position between a gate electrode and a drain electrode so that a part of the barrier layer corresponding to the position of the drain electrode has a small thickness.